R1120 rdc ? risc dsp communication 16-bit risc microcontroller specifications subject to change without notice, contact your sales representatives for the most update information. page 1 of 5 rev 1.0 june.14 2007 r r 1 1 1 1 2 2 0 0 b b r r i i e e f f s s h h e e e e t t 16-bit risc microcontroller
R1120 r r d d c c ? ? r r i i s s c c d d s s p p c c o o m m m m u u n n i i c c a a t t i i o o n n 16-bit risc microcontroller specifications subject to change without notice, contact your sales representatives for the most update information. page 2 of 5 rev 1.0 jul. 28 2005 1. features l five-stage pipeline l risc architecture l integrated pll (*1~*8) l maximum frequency: 80 mhz; the external bus, internal bus and core are operating in the same clock base l static & synthesizable design l bus interface - a multiplexed address and data bus which is compatible with the 80c186 microprocessor - supports a direct address bus a[19:0] - 1m-byte memory address space - 64k-byte i/o space l software is compatible with the 80c186 microprocessor l supports two asynchronous serial channels with hardware handshaking signals l supports cpu id l supports 32 pio pins l l l psram (pseudo static ram) interface with auto-refresh control l three independent 16-bit timers and one independent watchdog timer l the interrupt controller with seven maskable external interrupts and one non-maskable external interrupt l two independent dma channels l programmable chip-select logic for memory or i/o bus cycle decoder l programmable wait-state generators l the i/o pin output is 3.3 volt level and the input 3.3 to 5 volt tolerance. l 3.3v operation voltage l supports serial port/ dma transfers l with 8-bit or 16-bit boot rom bus size l a green product l package type - pqfp100 pins & lqfp100 pins
R1120 r r d d c c ? ? r r i i s s c c d d s s p p c c o o m m m m u u n n i i c c a a t t i i o o n n 16-bit risc microcontroller specifications subject to change without notice, contact your sales representatives for the most update information. page 3 of 5 rev 1.0 jul. 28 2005 2. block diagram dma unit psram control unit chip select unit refresh control unit bus interface unit pio unit timer control unit interrupt control unit clock and power management asynchro- nous serial port0 instruction queue (64bits) instruction decoder register file general, segment, eflag register alu (special, logic, adder, bsf) micro rom ea / la address control signal execution unit x1 x2 clkouta clkoutb int6~4 int0 tmrin0 tmrout0 tmrin1 tmrout1 drq0 drq1 txd0 rxd0 a[19:0] ad[7:0] ale rd_n vcc gnd lcs_n/once0_n mcs3_n/rfsh_n ucs_n/once1_n pcs5_n/a1 pcs6_n/a2 ardy srdy s2_n~s0_n dt/r_n den_n hold hlda s6/clkdiv2_n uzi_n rfsh2_n/aden_n wr_n wb_n asynchro- nous serial port1 rts0_n/rtr0_n cts0_n/enrx0_n txd1 rxd1 rts1_n/rtr1_n cts1_n/enrx1_n int1/select_n int3/inta1_n/irq int2/inta0_n nmi rst_n mcs[2:0] pcs3_n~pcs0_n pio[31:0] ao[15:8]
R1120 r r d d c c ? ? r r i i s s c c d d s s p p c c o o m m m m u u n n i i c c a a t t i i o o n n 16-bit risc microcontroller specifications subject to change without notice, contact your sales representatives for the most update information. page 4 of 5 rev 1.0 jul. 28 2005 3. package information pqfp100 pins 0.10 c seating plane 0.25 min a1 "a" d1 20.00 0.10 d 23.20 0.20 e1 14.00 0.10 e 17.20 0.20 "a" 0.65 bsc 0.25~0.38 unit:mm 1.60 ref 0.25 0.88 0.15 l l1 a2 2.85 0.12 detail a 3.40 max. 7 typ 15 typ detail a
R1120 r r d d c c ? ? r r i i s s c c d d s s p p c c o o m m m m u u n n i i c c a a t t i i o o n n 16-bit risc microcontroller specifications subject to change without notice, contact your sales representatives for the most update information. page 5 of 5 rev 1.0 jul. 28 2005 lqfp100 pins sealing plane 1 25 26 50 51 75 76 100 0.127(typ) "a" 0.08(max) 0.50(typ) 1.60(max) 1.00(ref) 0.2s(typ) gauge plane 16.00 0.15 14.00 0.10 16.00 0.15 14.00 0.10 1.40 0.05 0.10 0.05 0.22 0.05 0.60 0.15 0 ~ 7 unit:mm
|
